The present invention relates to semiconductor technologies, and more particularly to manufacturing for the fabrication of semiconductor devices.
In the field of semiconductor technology, including NAND-type flash memory semiconductor device having a broad application prospects. However, with decreasing integrated circuit (IC) feature size, the inventor has identified certain limitations in conventional technology. For example, isolation of the control gates and metal silicide formation on the control gate are two major challenges facing NAND-type flash memory, as explained below. FIGS. 1A to 1C are cross-sectional view diagrams illustrating a conventional method for silicide formation on the control gate, which includes the following steps:    Step E1: Form a control gate 101 and sidewalls 102 on a substrate 100. An interlayer dielectric 103 is formed on the device structure, as shown in FIG. 1A.    Step E2: Etch dielectric layer 103, sidewall 102, and control gate 101 to expose a portion of control gate 101, as shown in FIG. 1B;    Step E3: Form a silicide layer 104, as shown in FIG. 1C.
FIG. 1D is an SEM micrograph illustrating profiles of silicide formed using the conventional method. It can be seen that the silicide exhibits an undesirable profile, including protruding portions on the sidewalls. Therefore, these conventional solutions are not satisfactory and an improved method is needed.